1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device, and more particularly to a manufacturing method of a semiconductor device having gate insulation films of different thickness in the same substrate.
2. Description of the Related Art
Due to recent high integration and complication of function in semiconductor devices, special capabilities are generally requested therein. In a highly integrated semiconductor device, such as a device having a pitch of a half micron or less, the supply voltage must be in the range of 3.3 to 5 volts or less in order to reduce power consumption and to improve device reliability. For instance, supply voltages for micro processors or memory devices are already standardized to have low voltage supplies such as 2.5 or 3.3 volts. However, these low voltage devices are still used with high voltage devices, i.e., devices using 5 volts, to form an electronic system. Hence, to interface low voltage semiconductor devices with exterior devices requiring high voltage, high voltage transistors having gate insulation films with endurance to high voltage must be equipped within the low voltage semiconductor devices.
To ensure the reliability of the gate insulation films for high voltage, the gate insulation films of the high voltage transistors are thicker than those of low voltage transistors. However, these high voltage transistors have higher threshold current due to increased thickness of the gate insulation films. Every 10.sup..ANG. increase in the thickness of the gate insulation film results in 0.05 to 0.1 volt increases in threshold voltage. Therefore, impurity concentration for threshold voltage adjustment in high voltage transistors must be set differently to that in low voltage transistors.
To adjust the threshold voltage for transistors having different gate insulation film thickness on the same substrate, the conventional method was to set the impurity concentrations of the wells such that impurity concentration of the well for the high voltage transistor is different from that for the low voltage transistor. However, to optimize the threshold voltage for a respective NMOS transistor and a PMOS transistor having different gate insulation film thickness formed on the same substrate, four masking steps are required. More specifically, the above masking steps are, first masking step for forming a first P well where a low voltage NMOS transistor is to be formed; second masking step for forming a second P well where a high voltage NMOS transistor is to be formed; third masking step for forming a first N well where a low voltage PMOS transistor is to be formed; and fourth masking step for forming a second N well where a high voltage PMOS transistor is to be formed. Therefore, the manufacturing steps are complicated and the manufacturing period is quite long.